Technological Field
The described technology invention relates to the field of memory cells and memory arrangements. More particularly, the disclosed technology relates to non-volatile memory cells and memory arrangements thereof based on nano electromechanical switches.
Description of the Related Technology
For data cache and other memory operations such as used in L1, L2, L3 caches, scratchpad memories, GPU memory, today's often used memory is static random access memory SRAM. They form the main memory type inside logic chips.
SRAM memory cells suffer from a number of issues: they are energy-inefficient, both from a dynamic energy consumption perspective and from a leakage energy perspective. Even if standby leakage can be mitigated by recent state-of-the-art techniques, active leakage due to SRAM remains an issue. Furthermore, for both read and write operations, data typically is to be provided at a speed depending on the location of the memory in the memory hierarchy. For example, in L3 cache, up to 10 cycles may be used. For SRAM memory cells, typically a trade-off is made between speed, area and energy consumption. SRAM memory cells also are volatile, meaning that they lose their data when in a power-off state. Furthermore, SRAM memory cells typically use up large areas of the substrate, amongst others because they require large area per bit. An area reduction would be welcome.
A number of SRAM replacement options have been explored in the last years.
One set of solutions that has been considered are solutions based on emerging non-volatile memories such as STT-MRAM and RRAM.
In “Energy Efficient Many-core Processor for Recognition and Mining using Spin-based Memory,” IEEE Int'l Symp. on Nanoscale Architectures, June 2011, (pp. 122-128), R. Venkatesan et al. describes a specific processor having a memory based on Spin Transfer Torque Magnetic RAM (STT-MRAM). In “Relaxing Non-Volatility for Fast and Energy-Efficient STT-RAM Cache” (Smullen et al., IEEE Int'l Symp. on HPCA, February 2011, pp. 50-61), a design is described using only non-volatile memory (NVM) for cache memory, the non-volatile memory being STT-RAM. For optimal performance the properties of the STT-RAM are tuned, especially by relaxing the non-volatility condition. A refresh policy might be needed to hold the non-volatility. The paper “Resistive Computation: Avoiding the Power Wall with Low-Leakage, STT-MRAM Based Computing” (Xiaochen Guo et al., ISCA, 2010, pp. 371-382) presents a processor architecture in which most of the functionality is migrated from CMOS to STT-MRAM.
In general, compact non-volatile memory cells as now known have a read current flowing through the memory element so that no high performance read is possible. The current must be low enough to avoid cell state disturbance. Also the resistance level of the memory element must be selected in such a way that both read and write operations can be accommodated, which limit the options to improve read performance. Cells that avoid this current through the memory element typically are much less compact and often are not robust to transistor variations.
In European Patent Application No. 13198870.1, entitled “Nano-electro-mechanical based memory” and filed Dec. 20, 2013 in the name of IMEC, an SRAM replacement based on memory cells using a non-volatile NEM (nano electro-mechanical) switch is presented. In some implementations, the read current flows through the NEM switch may result in a slow reading step.
Consequently, there is still a need for a good SRAM replacement memory cell and corresponding memory arrangements.